1. Field of the Invention
The present invention relates to processors and associated address spaces. More specifically, the present invention relates to methods and apparatus for a processor to access address spaces of varying size.
2. Description of Related Art
Processors use address registers to access lines in an associated address space. The address registers can be configured with particular bit widths. Using smaller address registers and a corresponding smaller address space allows for the implementation of a smaller and less expensive processor. However, using larger address registers and a corresponding larger address space allows for a processor that can potential handle more data simultaneously. Where processor core size can be critical, such as on programmable chips, smaller address registers are often used.
Furthermore, data and functions are often stored in different memories or in different parts of the same memory. The sizes of these memories may vary. In conventional processors, program and data memories are often implemented on a single device. However, in digital signal processing (DSP) processors, program and data memories are frequently implemented on separate devices with separate buses. The program and data buses may have differing bit widths. Accordingly, the registers accessible by the processor core may have different bit widths.
Some processors (e.g., embedded processors) have restrictions on address register width in order to improve speed and resource utilization. Typically, the restriction imposed on address register width is used as a general restriction on address width accessible by the processor. However, the instruction set may offer a greater address range using immediate addressing. It is therefore desirable to provide improved methods and devices for generating code (e.g., instructions) that can take advantage of the larger address space even when the address space is limited by address register bit widths.